Refworks Account Login. Open Collections. UBC Theses and Dissertations. Featured Collection. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives.
It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. The architecture of the Viterbi decoder is bit-serial node-parallel.
The incoming 8-level quantized channel bits are input in parallel and converted to a serial stream. This reduces the amount of interprocessor wiring area substantially, as there are only single wire connections between the add-compare-select ACS units.
High decoding speed is still achieved because the ACS operation is carried out concurrentiy in each of the 16 states. For the path memory, the register exchange technique was adopted. To reduce the ICs silicon area, the path memory is full-custom layout. For the trellis interconnections between consecutive memory stages, a novel state relabelling technique is proposed that reduces the interconnect area substantially. The area savings are accomplished by redrawing the trellis as sets of butterflies, A major aspect of this IC is its very cost effective built-in self-test.
A novel test algorithm was developed for the path memory.
A specific but easy to generate test pattern is applied to the inputs. A major advantage of this deterministic test over pseudo-random techniques is that the test length is very short and, more importantly, independent of the number of states of the Viterbi decoder.
The rest of the circuit is tested by pseudo-random patterns combined with a multiple signature analysis scheme. After finding an appropriate initial state of the test pattern generator, it is possible to check for four identical signatures.
Compared to checking only one signature at the end of the test session, checking four identical signatures has the advantage of reducing the probability of error escape, while avoiding complicated signature checking for four different references. Moreover, test time can be reduced as faulty chips can be discarded as soon as a signature does not match the reference.
These advantageous features are accomplished with circuit overhead equal to checking only a single signature at the end of the test session. The only cost is a one-time logic simulation performed at design phase.
Introduction 1 1.
CDMA: Principles of Spread Spectrum Communication
Background 1 1. Contributions to Knowledge 2 1. Outline of Thesis 3 2. Convolutional Encoding and Viterbi Decoding 5 2.
Adaptive viterbi decoder pdf creator
Convolutional Codes 5 2. Convolutional Encoder 7 2. Code Evaluation 10 2. Punctured and Repetition Codes 10 2. Punctured Convolutional Codes 10 2.
Digital Communications: Viterbi Algorithm
Repetition Convolutional Codes 13 2. Viterbi Decoding 14 3. Viterbi Decoder Realization 21 3. Branch Metric Unit 21 3.
Decoder Architectures 22 3. Bit-Parallel Node-Parallel Architecture 22 3. Bit-Parallel Node-Serial Architecture 23 3.
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Shared Nodes Architecture 23 3. Bit-Serial Node-Parallel Architecture 24 3.
Path Metric Normalization 25 3. Variable Shift Normalization 26 3. Fixed Shift Normalization 26 3. Modulo Normahzation 26 3.
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Path Memory 28 3. Traceback Method 28 3. Register Exchange Technique 32 3. Design Implementation Options 34 3. Programmable Logic Devices 34 3.
Field Programmable Gate Arrays 36 3. Application Specific Integrated Circuit 38 4. Design of the Variable-Rate Viterbi Decoder 40 4. General Considerations 40 4. Branch Metric Unit 41 4. Add-Compare-Select Unit 42 4. Layout of Add-Compare-Select Units 45 4. Pairing of Add-Compare-Select-Units 52 4. Code Memory 58 4. Control Block 59 5.
Built-in Self-Test 60 5. Introduction to Built-in Self-Test 60 5. Multiple Signature Analysis 61 5. Fuzzy Multiple Signature Analysis 62 5. Minimal Hardware Multiple Signature Analysis 64 5. Test Algorithm for Path Memory 74 5. Output Data Evaluation 79 5.
Algorithm Performance 81 5. Test for the Add-Compare-Select Block 82 6. Prototype Chip 84 6. Chip Specifications 84 6. Design Tools 84 6. Pin Description 85 6. Chip Layout 89 6. Test Results 89 7. Conclusion 94 References 96 Appendix A.
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Cell Layouts Appendix B. List of Acronyms List of Figures Figure 2. A tail is appended to clear the encoder. Samir Kallel for their constant encouragement and valuable guidance I was fortunate to receive in the past year. Their helpful comments and critical questions made research interesting for me.
I would also like to thank my colleague Yuejian Wu for his helpful discussions on ideas how to implement efficient built-in self-tests. Especially, I thank Yuejian for letting me implement his idea of multiple signature analysis, which improved the test quality dramatically. Without his help it would not have been possible to finish the design and layout of the chip in a reasonable time.
Dave had quick solutions to almost any problem relating the use of our VLSI tool.
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Here, I would like to thank the Canadian Microelectronics Corporation for providing me both hardware and software tools for VLSI design and providing me access to Northern Telecom's fabrication process. I also want to thank the Austrian Government and the Austrian Federal Chamber of Commerce for their financial support that made this work possible.
I would like to express my sincere thanks to my girlfriend Claudia Kiinzel, who paved the way to the successful completion of this project with her love and support. I am extremely grateful to my parents, who always encourage and support whatever I do. Without them nothing would have been possible.
Introduction 1. In recent years there has been a great interest in convolutional codes and their use in modern communications systems. Convolutional codes can be used solely for forward error correction FEC , or can be incorporated into transmission systems using automatic-repeat-request ARQ schemes to ensure error-free transportation of data.
The advent of high-rate punctured convolutional codes has incresed the interest in convolutional coding, as punctured codes can be readily decoded and still offer substantial coding gain. Variable-rate FEC systems use a family of punctured convolutional codes derived from the same low-rate mother code.
With a type II hybrid A R Q protocol, in addition to a block code that is used for error detection only, a second code, usually a convolutional code, is used for error correction [Kal93]. To improve the system throughput, variable code rates can be used [Hag88], [Kal90], [Kal93]. The chosen code rate depends on the channel condition, round trip delay of the data packets, and buffer size at the receiver.